1. Field of the Invention
Generally, the present disclosure relates to integrated circuits including advanced transistor elements, one type of which comprises a channel semiconductor alloy, such as a silicon/germanium alloy.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally transistor performance may also be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. The threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has also been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately adapt the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes in an advanced stage for adjusting the work function and thus the threshold voltages in a very advanced process stage.
Although the process strategy for providing a threshold adjusting semiconductor material in an early manufacturing stage, thereby enabling the adjustment of the electronic characteristics of sophisticated gate electrode structures in an early manufacturing stage, may present a very promising process strategy, it turns out, however, that nevertheless significant transistor non-uniformities may be introduced, in particular in isolation regions when incorporating the channel semiconductor alloy selectively in one type of active region, thereby significantly affecting the further processing, such as the patterning of the gate electrode structures, forming spacer elements and finally completing the transistor configuration, possibly in combination with additional interlayer dielectric materials, which may also have to be formed above the isolation regions having the increased surface topography.
With reference to FIGS. 1a-1h, a typical conventional process flow will now be described in order to illustrate the problems involved in forming a channel semiconductor alloy in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a silicon-based semiconductor layer 102, which may be a portion of a crystalline substrate material of the substrate 101, when a bulk configuration is considered. The semiconductor layer 102 is laterally delineated in a plurality of active regions, i.e., semiconductor regions in and above which transistors are to be formed. For convenience, a first active region 102A and a second active region 102B are illustrated in FIG. 1a and these active regions are laterally delineated by an isolation region 102C, such as a shallow trench isolation. In the example shown, the active region 102A corresponds to a semiconductor region in and above which a transistor is to be formed, which does not require the incorporation of a specific channel semiconductor material, while on the other hand the active region 102B corresponds to the semiconductor region of a transistor in which an appropriate channel semiconductor material is to be formed, for instance in the form of a silicon/germanium alloy, as is also discussed above. Furthermore, in the manufacturing stage shown, a pad oxide layer 103, i.e., a thin silicon dioxide material, is formed on the active regions 102A, 102B, followed by a silicon nitride layer 104.
The semiconductor device 100 is typically formed on the basis of the following process strategy. At an initial manufacturing stage, the layers 103 and 104 are provided, for instance, by performing an oxidation process in order to obtain the layer 103 with a desired thickness, for instance in the range of 5-8 nm, followed by a deposition process for providing a silicon nitride material having a thickness of 10-20 nm, depending on the further processing. To this end, any well-established deposition recipes are applied. Thereafter, sophisticated lithography techniques are used in order to form an etch mask (not shown), which in turn defines the lateral position, size and shape of corresponding trenches to be formed in the semiconductor layer 102. To this end, the silicon nitride layer 104 is patterned to receive corresponding trenches and the layer is then used as a hard mask for etching through the pad oxide 103 and into the semiconductor material of the layer 102. Thereafter, the trenches are filled with an appropriate dielectric material, such as silicon dioxide, possibly in combination with any oxidation processes, wherein any excess material is removed by chemical mechanical polishing (CMP), wherein the silicon nitride material 104 acts as an efficient stop material. Due to a difference in the removal rate, a certain degree of recessing of the isolation structure 102C may be created, as illustrated in FIG. 1a. 
FIG. 1b schematically illustrates the device 100 after the removal of the silicon nitride material 104 (FIG. 1a), which is accomplished on the basis of selective etch chemistries, such as hot phosphoric acid, possibly in combination with APM (ammonium hydroxide/hydrogen peroxide mixture). It should be appreciated that the isolation regions 102C may still exhibit a substantially uniform surface topography.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, appropriate dopant species 106A, 106B are incorporated into the active regions 102A, 102B in order to adjust the overall transistor characteristics. For example, appropriate well dopant species, threshold voltage adjusting species and the like are incorporated into the active regions 102A, 102B by applying any appropriate masking regime in combination with corresponding implantation techniques. For example, a resist mask 105 is illustrated so as to cover the active region 102B and a portion of the isolation region 102C, while an ion implantation process 106 performs so as to incorporate one or more dopant species, such as the species 106A. Thus, a plurality of resist removal processes have to be applied in combination with corresponding cleaning recipes, which may typically cause a certain degree of material erosion in the pad oxide layer 103 and also in the isolation regions 102C. Due to certain alignment inaccuracies, in particular in the isolation region 102C, that laterally separates active regions of inverse conductivity type, such as the regions 102A, 102B, minor inaccuracies during the formation of the corresponding resist masks may result in a certain degree of recessing (not shown) which typically results in a certain surface topography.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a hard mask material 108, such as an oxide material, a silicon nitride material and the like, is formed above the active regions 102A, 102B and also above the isolation region 102C. To this end, any appropriate deposition technique may be applied, such as plasma assisted chemical vapor deposition (CVD), thermally activated CVD and the like. Moreover, a resist mask 107 is formed above the mask layer 108 in order to cover a portion thereof formed above the active region 102A.
FIG. 1e schematically illustrates the device 100 in a manufacturing stage in which the mask layer 108 is patterned so as to expose the second active region 102B. To this end, any well-established etch recipes are applied in which the resist mask 107 of FIG. 2d is used as an etch mask. Depending on the etch recipe used and moreover depending on the type of material used in the hard mask 108, a pronounced degree of recessing may occur in any exposed isolation regions and also in a corresponding exposed portion of the isolation region 102C, as indicated by 102R. Moreover, a corresponding resist removal process and a cleaning recipe may be applied, which may also contribute to the recess 102R.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a silicon/germanium material layer 110 is formed on the active region 102B and may thus represent a part thereof so as to enable continuing the further processing on the basis of the region 102B having the desired band gap difference with respect to the active region 102A, as may be required for performing complex gate electrode structures, as is also discussed above.
The device 100 as shown in FIG. 1f is typically formed by exposing the device 100 as shown in FIG. 1e to at least a further cleaning process, which may result in a further recessing of the isolation region 102C, since typically oxide-consuming etch recipes may be applied. In some cases, prior to forming the silicon/germanium alloy 110, a certain degree of recessing, i.e., material removal of the active region 102B, is applied in order to provide superior growth conditions during the subsequent selective epitaxial growth process. Also in this case, the recess 102R may increase in depth, thereby generating a pronounced surface topography with respect to portions of the isolation region 102C, which are still covered by the hard mask 108. Next, the material layer 110 is deposited, which is typically accomplished by using well-established selective epitaxial growth recipes in which process parameters are adjusted such that a pronounced material deposition may be restricted to crystalline surface areas, while a significant material deposition on dielectric surface areas, such as the isolation regions 102C and the hard mask 103, is suppressed. For example, the silicon/germanium layer 110 may be formed with a thickness of 8-12 nm, while germanium contents may be up to 25 atomic percent, depending on the required electronic characteristics of the active region 102B.
FIG. 1g schematically illustrates the device 100 in a further advanced manufacturing stage, i.e., after the removal of the hard mask 108 and the pad oxide 103 (FIG. 1f), which is typically accomplished by using selective etch recipes, such as hot phosphoric acid and the like when silicon nitride is to be removed and hydrofluoric acid (HF) when a silicon oxide material is to be etched. Consequently, during the corresponding process sequence, also material of the isolation structure 102C may be consumed. In order to reduce the pronounced surface topography, additional mask layers may frequently be applied which, however, may result in more complex surface topography, although the absolute depth of the recesses 102R may be reduced to a certain degree. Consequently, the resulting surface topography 102S may be determined by the preceding processes and may result in a non-symmetric structure, which may still have formed therein recesses 102R with significant depth, although traditional complex masking regimes and corresponding etch techniques may have been applied, for instance by masking the active region 102B during one or more of the etch processes for exposing the active region 102A.
Consequently, the further processing is to be continued on the basis of the pronounced surface topography 102S, which in turn may result in non-uniformities of complex gate electrode structures and thus of any transistors formed in and above the active regions 102A, 102B.
FIG. 1h schematically illustrates the device 100 according to some illustrative examples in a further advanced manufacturing stage. As shown, a transistor 150A is formed in and above the active region 102A and comprises a gate electrode structure 160A. Similarly, a second transistor 150B is formed in and above the active region 102B, which comprises the semiconductor alloy 110. As discussed above, the gate electrode structures 160A, 160B may have a complex configuration, for instance comprising a conventional silicon dioxide-based gate dielectric material 161 in combination with a high-k dielectric material 162, wherein an electrode material, such as titanium nitride, possibly in combination with an additional work function metal species 163, is provided. Furthermore, a semiconductor-based electrode material 164 is typically incorporated in the gate electrode structures 160A, 160B. Moreover, any appropriate spacer structure 165 may be formed on sidewalls of the materials 164, 163, 162 and 161 in order to ensure integrity of these materials and also provide an appropriate mask for forming drain and source regions 151 in the active region 102A. The gate electrode structure 160B may have a similar configuration, however, if required, the layers 162 and/or 163 may differ from the corresponding layers in the gate electrode structure 160A, for instance with respect to the incorporation of any work function metal species, while additionally the semiconductor alloy 110 may provide the desired overall threshold voltage of the transistor 150B. For example, the transistor 150B is a P-channel transistor, while the transistor 150A is an N-channel transistor. The transistors 150A, 150B are formed on the basis of highly complex process techniques which require the deposition and patterning of the layers 161, 162 and 163 so as to comply with a corresponding conductivity type of the transistors 150A, 150B. Thereafter, the electrode material 164 is formed, possibly in combination with additional hard mask materials and the like, followed by a complex lithography process and patterning strategy in order to obtain the gate electrode structures 160A, 160B with a gate length of, for instance, 50 nm and less. It should be appreciated that in particular the deposition and patterning of the materials 162, 163 and also the subsequent patterning of the final gate layer stack may significantly depend on the overall surface topography, wherein, in particular, the pronounced surface topography of the isolation region 102C may contribute to process non-uniformities, which in turn may result in a shift of transistor characteristics, such as gate length, threshold voltage and the like. Similarly, during the further processing, the surface topography essentially created during the formation of the silicon/germanium alloy 110 may also affect the configuration of the spacer structure 165, which in turn may influence the finally obtained dopant profiles of the drain and source regions 151.
It should further be appreciated that, in sophisticated applications, frequently a strain-inducing semiconductor material, such as a silicon/germanium material (not shown), may be incorporated in some active regions, such as the active region 102B, wherein the corresponding process sequence may contribute to an even further pronounced surface topography, which may contribute to a more non-symmetric profiling of the corresponding isolation region 102C.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.